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preliminary data sheet ac208 ac208-ds04-405-r 16215 alton parkway ? p.o. box 57013 irvine, california 92619-7013 phone: 949-450-8700 fax: 949-450-8710 07/08/02 2.5v 10/100-tx 8-port repeater/7+1 uplink port with integrated bridge figure 1: functional block diagram general description features the ac208 is an unmanaged eight-port 10/100 mbps repeater with an integrated bridge. the ac208 provides a low-cost and integrated solution for unmanaged repeater applications. the ac208 is a class ii repeater. in addition, the eighth port supports 10/100 tx interface for uplink function. the ac208 provides 10/100 mbps auto-negotiation and parallel detection for all ports. in addition, the option to configure each transceiver port via the eeprom interface is available. the ac208 provides two internal repeater state machines, one operating at 10 mbps and the other at 100 mbps. once the technology is set, the device automatically connects each port to the appropriate repeater segment. the ac208 provides two back-planes for expansion, one operates at 10 mbps and the other operates at 100 mbps. up to 32 ports can logically be connected into one repeater using back-plane buses. the ac208 integrates repeater and bridge technologies with store-and-forward mechanisms. features ? low-power (less than 1a total current consumption when used with 1.25:1 transformer) eight-port 10/100 mbps repeater with built-in bridge function. mdc/mdio for control/status of transceiver components. eight integrated 10/100 mbps ieee 802.3u compliant transceivers. ieee 802.3u-compliant auto-negotiation. fully integrated adaptive equalizer provides phase/ amplitude compensation for various cable lengths up to 30 db at 100 mhz. patent-pending dc restoration technique reduces offset/ baseline wander. unique scrambler seed for all ports for better emi. cascadable backplanes compatible with ac206. non-blocking 10/100m bridge with mac and bridge. one segment of a bridge is fixed to 100 mbps, while the other segment can be configured for 10 or 100 mbps. bridge functions include: - embedded 32 kb of memory for address table and packet buffer. - local mac address filtering. - xor hashing scheme. - short routing decision time. - forwarding schemes: store-and-forward. - address table up to 1k entries. programmable led display for activity, link, speed, partition, utilization, and collision rate. advanced power management includes: - each transceiver port can be turned off independently. - standby mode, which reduces power when the port is not connected. low-power 2.5v 0.25 m cmos implementation with 128-pin qfp package. input tolerance to 3.3v. mux p h y r_100 r_10 bridge 10m 100m . . . . . . p h y p h y p h y mii mii rbp 256kbits ram tx0 tx1 tx2 tx7 up link p h y tx3 p h y tx4 p h y tx5 p h y tx6 10m rbp 100m rbp 100m rbp 10m rbp
altima communications, inc. a broadcom company broadcom corporation p.o. box 57013 16215 alton parkway irvine, ca 92619-7013 ? 2002 by altima communications, inc. all rights reserved printed in the u.s.a. broadcom ? and the pulse logo ? are trademarks of broadcom corporation and/or its subsidiaries in the united states and certain other countries. all other trademarks are the property of their respective owners. this data sheet (including, without limitation, the broadcom component(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass tran sportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as-is", without warranty of any kind. broadcom disclaims a ll warranties, expressed and implied, including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement. r evision h istory revision date change description ac208-ds04- 405-r 07/08/02 incorporate mdc/mdio changes. ac208-ds03-r 06/07/02 general technical revision. ac208-ds02-r 06/20/01 updated the following tables: ?led connections? ?power and ground? ?register set? ?bridge control register? ?bt control register? ?led effect with partition/isolation event? ?eeprom? ac208-ds01-r 02/08/01 updated ?scrambler? in the ?functional description? section to: when the bt control register 23.11 is set to 1 the data scrambling function is disabled, the 5-bit data stream is clocked directly to the device?s pma sublayer. added pin #114 to dgnd in the ?power and ground? table. added pins # 28, 29, 30, 31, 33, 34, 35, 38 to the ?no connects? table. updated the ?electrical characteristics? section (replaced the digital input voltage ?0.5v to vcc with ?0.5v to 3.3v ) updated the ?digital timing characteristics? section various text changes throughout the whole document. added the ?mechanical information? section, outlining the packaging specifications. updated ?led timing.? AC208-DS00-R 10/9/00 initial release.
broadcom document ac208-ds04-405-r page iii preliminary data sheet ac208 07/08/02 t able of c ontents section 1: functional description ...................................................................................... 1 functional description ............................................................................................................................... .1 clocks, reset, and power management functions .................................................................................. 1 media independent interface .................................................................................................... .............. 2 scrambler...................................................................................................................... .......................... 2 parallel to serial and nrz?nrzi to mlt-3 conversion ........................................................................ 2 pll clock synthesizer.......................................................................................................... .................. 3 receive function ............................................................................................................................... .......... 3 adaptive equalizer ............................................................................................................. ..................... 3 link monitor ................................................................................................................... ......................... 4 baseline wander compensation ................................................................................................... ......... 4 clock/data recovery ............................................................................................................ .................. 4 decoder/descrambler ............................................................................................................ ................. 4 auto-negotiation and miscellaneous functions ....................................................................................... 5 parallel detection............................................................................................................. ....................... 5 carrier sense/rxdv for mii port only........................................................................................... ......... 5 cable length monitor ............................................................................................................................... ... 5 media independent interface .................................................................................................... .............. 6 forwarding scheme .............................................................................................................. .................. 6 address recognition............................................................................................................ ................... 6 reset and restart .............................................................................................................. ..................... 6 media access control ........................................................................................................... .................. 6 hardware configuration ......................................................................................................... ................. 7 software configuration ......................................................................................................... .................. 7 leds ........................................................................................................................... ............................ 7 address table .................................................................................................................. ....................... 9 routing decision............................................................................................................... .................... 10 learning process ............................................................................................................... ................... 10 aging time ..................................................................................................................... ....................... 10 forwarding scheme .............................................................................................................. ................ 11 bridge buffer management and queues ............................................................................................ .. 11
broadcom page iv document ac208-ds04-405-r ac208 preliminary data sheet 07/08/02 section 2: pins ................................................................................................................... 12 pin descriptions ............................................................................................................................... ..........12 section 3: register descriptions ..................................................................................... 18 register description ............................................................................................................................... ....18 bridge configuration register .................................................................................................. .............22 phy configuration register ..................................................................................................... .............23 phy identifier 2 register ...................................................................................................... .................25 auto-negotiation advertisement register ........................................................................................ .....25 auto-negotiation expansion register............................................................................................ ........26 cable length register.......................................................................................................... .................30 power management register ...................................................................................................... ..........31 led effect with partition/isolation event ...................................................................................... .........33 led effect with link event ..................................................................................................... ...............33 led effect with auto-negotiating event ......................................................................................... .......34 led register control mode...................................................................................................... .............35 led display matrix ............................................................................................................................... ......38 system considerations.......................................................................................................... ................38 section 4: electrical characteristics ............................................................................... 39 absolute maximum ratings .......................................................................................................................39 operating range ............................................................................................................................... ..........39 refclk pins .................................................................................................................... ....................40 i/o characteristics?led pins ................................................................................................... ...........40 10base-t transceiver characteristics ........................................................................................... ......41 section 5: digital ti ming characteristics ....................................................................... 42 power on reset ............................................................................................................................... ............42 phy mdc/mdio interface ...........................................................................................................................43 100 mbps repeater backplane receive/transmit timing .....................................................................44 10 mbps repeater backplane receive/transmit timing .......................................................................45 eeprom interface timing .........................................................................................................................46 led timing ............................................................................................................................... ...................47 tx application termination .......................................................................................................................48
broadcom document ac208-ds04-405-r page v preliminary data sheet ac208 07/08/02 section 6: mechanical information ................................................................................... 49 section 7: ordering information .......................................................................................50
ac208 preliminary data sheet 07/08/02 broadcom page vi document ac208-ds04-405-r l ist of t ables table 1: led connections........................................................................................................ ..................... 8 table 2: content of address lookup table ........................................................................................ ........... 9 table 3: embedded memory structure.............................................................................................. ..........11 table 4: media dependent interface pins (tx) .................................................................................... .......12 table 5: eeprom interface ....................................................................................................... .................13 table 6: mdc/mdio interface ..................................................................................................... ................13 table 7: 100 mbps internal repeater ............................................................................................. .............14 table 8: 10 mbps internal repeater bus .......................................................................................... ...........15 table 9: led pins............................................................................................................... .........................16 table 10: configuration and setup............................................................................................... .................17 table 11: clock reset ........................................................................................................... ........................17 table 12: power and ground ...................................................................................................... ..................17 table 13: no connects........................................................................................................... .......................17 table 14: register set.......................................................................................................... .........................18 table 15: phy port status register .............................................................................................. ................20 table 16: phy port status ....................................................................................................... .....................20 table 17: initial device configuration register ................................................................................. ............21 table 18: bridge configuration register ......................................................................................... ..............22 table 19: phy configuration register 0 .......................................................................................... .............23 table 20: phy status register 1................................................................................................. ..................24 table 21: phy identifier 1 register ............................................................................................. ..................25 table 22: phy identifier 2 register ............................................................................................. ..................25 table 23: auto-negotiation advertisement register ............................................................................... ......25 table 24: auto-negotiation link partner ability register ........................................................................ ......26 table 25: register 6: auto-negotiation expansion register ....................................................................... ..26 table 26: auto-negotiation next page transmit register.......................................................................... ...27 table 27: phy 10base-t configuration register ................................................................................... .....28 table 28: phy interrupt control/status register................................................................................. ..........29 table 29: diagnostic register ................................................................................................... ....................30 table 30: cable length register ................................................................................................. ..................30 table 31: receive error count ................................................................................................... ...................31 table 32: power management register ............................................................................................. ...........31
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r page vii table 33: transceiver mode register ............................................................................................. .............. 32 table 34: led effect with partition/isolation event............................................................................. .......... 33 table 35: led effect with link event............................................................................................ ................ 33 table 36: led effect with activity (crs) event .................................................................................. .......... 34 table 37: led effect with auto-negotiating event................................................................................ ........ 34 table 38: led effect with speed100 event ........................................................................................ .......... 35 table 39: led register control mode ............................................................................................. ............. 35 table 40: eeprom................................................................................................................ ....................... 36 table 41: 4b/5b code-group table................................................................................................ .............. 37 table 42: total power consumption............................................................................................... .............. 39 table 43: ttl i/o characteristics ............................................................................................... .................. 40 table 44: refclk pins ........................................................................................................... ..................... 40 table 45: i/o characteristics?led pins .......................................................................................... ............ 40 table 46: 100base-tx transceiver characteristics ................................................................................ .... 41 table 47: 10base-t transceiver characteristics.................................................................................. ....... 41 table 48: power on reset........................................................................................................ ..................... 42 table 49: phy mdc/mdio interface ................................................................................................ ............ 43 table 50: 100 mbps repeater backplane receive/transmit timing............................................................ 44 table 51: 10 mbps repeater backplane receive/transmit timing.............................................................. 45 table 52: eeprom interface timing............................................................................................... ............. 46 table 53: led timing ............................................................................................................ ....................... 47 table 54: package dimensions for the ac208 ...................................................................................... ....... 49 table 55: ordering information .................................................................................................. ................... 50
ac208 preliminary data sheet 07/08/02 broadcom page viii document ac208-ds04-405-r l ist of f igures figure 1: functional block diagram.............................................................................................. ................... i figure 2: exclusive or hashing algorithm ........................................................................................ .............10 figure 3: address learning and recognition ...................................................................................... .........10 figure 4: basic memory management concept ....................................................................................... ....11 figure 5: led display matrix .................................................................................................... ....................38 figure 6: power on reset ........................................................................................................ .....................42 figure 7: phy mdc/mdio interface................................................................................................ .............43 figure 8: 100 mbps rbp receive/transmit timing.................................................................................. ....44 figure 9: 10 mbps rbp receive/transmit timing................................................................................... .....45 figure 10: eeprom interface timing .............................................................................................. ..............46 figure 11: led timing........................................................................................................... .........................47 figure 12: application termination .............................................................................................. ...................48 figure 13: 128-pin pqfp ......................................................................................................... ......................49
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r functional description page 1 section 1: functional description f unctional d escription the ac208 is an unmanaged 10/100 mbps repeater with int egrated bridge functions. the device provides eight 10/100base-tx twisted pair interface ports. the ac208 also includes a built-in two-segment bridge for 10/100 mbps connection. the ac208 provides the highest integration chip solution for dual speed hub systems. the result is ultra low power consumption that consumes less than 1a maximum when all ports are running 100base-tx full-speed. the built-in function powers down when not used (no cable detected). th is reduces power consumption and improves long-term reliability. c locks , r eset , and p ower m anagement f unctions the ac208 requires a single 25-mhz clock signal at the clk input pin. an internal pll generates all of the clock frequencies needed by the device from the single clock input. the ac208 can be reset in two ways: during initial power on. hardware reset: a logic low signal of 10 s pulse width applies to rst pin. during reset, all mode pins latch in, the internal address table is initialized, and the internal state machine is reset to kno wn states. at the completion of the reset sequence, all ports are enabled for frame reception and transmission. the ac208 offers the following power management: power down mode: this can be achieved by writing to register 0.11 plus port based address. example: port 1 has a based address of hex 00. during power down, the device is able to respond through the mdc/ mdio interface. energy detect mode: the device powers down all of the unused circuitry when the cable is not installed. the energy detect (ed) circuit stays on to monitor incoming signals from the media. the mdc/mdio interface is turned on in response to any access transaction. the transmit circuit sends out a link pulse with minimum power consumption. if a valid signal is received from the media, the device is powered up and resumes normal transmit/receive operation.
ac208 preliminary data sheet 07/08/02 broadcom page 2 transceiver and transmit function document ac208-ds04-405-r t ransceiver and t ransmit f unction in 100base-tx mode, the transceiver transmits mlt-3 signal to the cable via isolation transformer. mlt-3 data is a three level signal data. this data is scrambled when transmitted to the media. the mlt-3 data is synchronous to the 25-mhz clock . in 10base-t mode, manchester code is generated by the 10b ase-t core logic, which synthesizes through the output waveshaping driver. this helps reduce any emi emission, which eliminates the need for an external filter. m edia i ndependent i nterface the media independent interface (mii) is for direct connection of an external device to the repeater. the transmit data on the mii interface is 4-bit nibbles at 25/2.5 mhz rate. this mii interface is connected to the repeater via the mii txd lines. t he external device asserts tx_en during transmission, or forces an error in the encoded data using tx_er. s crambler in 100base-tx mode, the internal 5-bit transmit data stream is scrambled as defined by the tp-pmd stream cipher function in order to reduce radiated emissions on the twisted pair cable. the scrambler encodes a plain text nrz bit stream using a key stream periodic sequence of 2047 bits generated by the recursive linear function: x [n] = x [n-11] + x [n-9] (modulo 2) the scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range, thus eliminating peaks at a single frequency. emi emission can be further reduced by assigning a unique scrambled seed to each port. when the base-t control register 23.11 is set to 1 the data scrambling function is disabled, the 5-bit data stream is clocked directly to the device?s pma sublayer. p arallel to s erial and nrz?nrzi to mlt-3 c onversion the internal 5-bit nrz data is clocked into transceiver?s shift register with a 25 mhz clock, and clocked out with a 125 mhz clock to convert it into a serial bit stream. both clocks are generated by an on-chip clock synthesizer, and they are in sync to each other. the serialized data is further converted from nrz to nrzi format, which produces a transition on every logic 1 and no transition on logic 0. to further reduce emi emission, the nrzi data is converted to mlt-3 signal. the effect offers a 3 db to 6 db reduction in emi emissions over an un-converted nrzi signals, thus increases the output signals? margin of operating within the fcc class b limit. when there is a transition occurring in nrzi data, there is a corresponding transition for mlt-3 data. for nrzi data, it changes the count up/down direction after every single transition. for mlt-3 data, it changes the count up/down direction after every two transitions. the nrzi to mlt-3 data conversion is implemented without reference to the bit timing or clock information. the conversion requires detecting transition of the incoming nrzi data and set up the count up/down direction for the mlt-3 data. asserting fx_sel high bypasses this encoding.
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r receive function page 3 m ultimode t ransmit d river the multimode driver transmits mlt-3 coded signal in 100base-tx mode and manchester coded signal in 10base-t mode. the slew rate of the transmitted mlt-3 signal can be controlled to eliminate high frequency emi component. the mlt-3 signal after the magnetic has a typical rise/fall time of approximately 4 ns, which is within the target range specified in the ansi tp- pmd standard. in 10base-t mode, high frequency pre-emphasis is performed which extends the cable-driving distance without the need of an external filter. flp/nlp also drives signals through the 10base-t driver. the 10base-t and 100base-tx transmit signals are multiplexed to the transmit output driver. this a rrangement results in using the same external transformer for both the 10base-t and the 100base-tx. the driver output level is set by a built-in bandgap reference and an external resistor connected to the ribb output pin. the resistor sets the output current for all modes of operation. each of the txop/ n outputs is an open drain device which has a source resistance of 10 ? maximum and a current rating of 40 ma for the 2 v p-p mlt-3 signal, 100 ma for 5v p-p manchester signal when used 1:1 transformer. pll c lock s ynthesizer the transceiver also includes on-chip pll clock synthesizer that generates a 125-mhz and a 25-mhz clock for the 100base-tx, or a 100-mhz and 20-mhz clock for the 10base-t and auto-negotiation operations. the pll clock generator uses a fully differential vco cell that induces a very low jitter. the zero dead zone phase detection method implemented in this design provides excellent phase tracking. a charge pump with charge sharing compensation is also included to further reduce jitter at different loop filter voltages. on-chip loop filter eliminates the need for external components and avoids external noise pickup. only one external 25-mhz crystal or a signal source is required as a reference clock. r eceive f unction in 100base-tx mode, the receive function implements the reverse order function in the transmit path. it includes a receiver with adaptive equalization and dc restoration, mlt-3 to nrzi conversion, data and clock recovery at 125 mhz, nrzi to nrz conversion, serial-to-parallel conversion, de-scrambling, and 5b to 4b decoding. the receiver circuit starts with a dc bias for the differential rx inputs, follows with a low-pass filter to filter out high frequency noise from the transmission channel media. an energy detect circuit is also added to determine whether there is any signal energy on the media. this is useful in the power-saving mode. the amplification ratio and slicer threshold is set by the on-chip bandgap reference. in 10base-t mode, signal first passes through a third order lowpass filter, which filters all the noise from the cable, board, and transformer. this eliminates the need for a 10base-t external filter. a manchester decoder and a serial-to parallel follows to generate the 4-bit data in mii mode. a daptive e qualizer each of the eight transceivers is designed to accommodate for maximum cable length of 150m utp cat5 cable. a 150m of utp cat-5 cable (such as at&t 1061) has an attenuation of 31 db at 100 mhz. a typical attenuation of a 100m cable is 20 db. the worst case attenuation is around 24?26 db defined by tp-pmd. the amplitude and phase distortion from the cable causes inter-symbol interference (isi) which makes clock and data recovery impossible. adaptive equalizer is done by matching the inverse transfer function of the twist-pair cable. this is a variable equalizer that changes its equalizer frequency respons e in accordance to cable length. the cable length is estimated based on comparisons of incoming signal strength against some the known cable characteristics. the equalizer has a monotonically frequency response, and tunes itself automatically for any cable length to compensate for the amplitude and phase distortion incurred from the cable.
ac208 preliminary data sheet 07/08/02 broadcom page 4 receive function document ac208-ds04-405-r l ink m onitor signal levels are detected through a squelch detection circuitr y. a signal detect (sd) circuit follows the equalizer and is asserted high when the peak detector detects a post-equalized signal with peak to ground voltage level larger than 400 mv. this is approximately 40% of a normal signal voltage level. in addition, the energy level must be sustained longer than 2~3 s in order for the signal detects be asserted. it gets de-asserted approximately 1~2 s after the energy level is consistently less than 300 mv from peak to ground. in 100base-tx mode, when no signal or invalid signal is detected on the receive pair, the link monitor enters in the link fail state where only scrambled idle code is transmitted. when a valid signal is detected for a minimum period of time, the link monitor enters a link pass state and transmit and receive functions are entered. in 10base-t mode, a link-pulse detection circuit constantly m onitors the rxip/rxin pins for the presence of valid link pulses. b aseline w ander c ompensation the 100base-tx data stream is not always dc balanced. the transformer blocks the dc component of the incoming signal, thus the dc offset of the differential receives inputs can wander. the shift in the signal levels, coupled with non-zero rise and fall times of the serial stream can cause pulse-width distortion, creating jitter and possible increases in error rates. therefore, a dc restoration circuit is needed to compensate for the attenuation of dc component. the transceiver implemented is a patent-pending dc restoration circuit, unlike the traditional implementation; it does not need the feedback information from the slicer and clock recovery. this not only simplifies the system/circuit design but also eliminates any random/systematic offset on the receive path. in 10base-t mode, the baseline wander correction circuit is not required and is bypassed. c lock /d ata r ecovery the equalized mlt-3 signal passes through a slicer circuit that converts to nrzi format. the transceiver uses a mixed-signal phase locked loop (pll) to extract clock information of the incoming nrzi data. the extracted clock is used to re-time the data stream and set the data boundaries. the transmit clock is locked to the 25-mhz clock input while the receive clock is locked to the incoming data streams. when initial lock is achieved, the pll switches to lock to the data stream, extracts a 125-mhz clock and uses that for bit framing to recover data. the recovered 125-mhz clock is also used to generate an internal 25-mhz rx_clk. the pll requires no external components for its operation and has high noise immunity and low jitter. it provides fast phase align (lock) to data in one transition and its data/clock acquisition time after power-on is les s than 60 transitions. the pll can maintain lock on run-lengths of up to 60 data bits in the absence of signal transitions. when no valid data is present (like when the sd is de-asserted), the pll switches back to lock with tx_clk and provides a continuously running rx_clk. d ecoder /d escrambler the descrambler detects the state of the transmit linear feedback shift register (lfsr) by looking for a sequence representing consecutive idle codes. the descrambler acquires lock with the data stream by recognizing idle bursts of 30 or more bits and locking to its de-ciphering linear feedback shift register (lfsr). once lock is acquired, the device operates with the inter- packet-gap (ipg) as low as 40 ns . before lock occurs, the de- scrambler requires a minimum of 720 ns of idle in between packet in order to acquire lock. the deciphering logic also tracks the number of consecutive receive errors detected while rx_dv is asserted. once the error counter exceeds its limit (currently set to 64 consecutive errors), the logic assumes that lock has been lost, and the de - cipher circuit resets itself. the process of regaining lock begins again. stream cipher de-scrambler is not used in 10base-t mode.
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r auto-negotia tion and miscellaneous functions page 5 a uto -n egotiation and m iscellaneous f unctions each of the transceivers contain the ability to negotiate its mode of operation over the twisted pair using the auto-negotiatio n mechanism defined in the clause 28 ieee 802.3u specification. auto-negotiation may be disabled by software via eeprom. the transceiver automatically chooses its mode of operation by detecting the incoming signal. during auto-negotiation, the auto-negotiation advertisement register is sent to its link partner through a series of fast link pulse (flp). when auto-negotiation enabled, transceiver sends flp during the following conditions: power on link loss restart command at the same time, the device monitors incoming data to determine its mode of operation. parallel detection circuit is enabled as soon as 10base-t idle or 100base-tx idle is detected. the mode of operation is configured based on the technology of the incoming signal. when the device receives a burst of flp from its link partner with three identical link code words (ignoring acknowledge bit), it stores these code words in the auto-negotiation link partner ability register and waits for the next three identical code words. once the device detects the second code word, it configures itself to the highest technology that is common to both ends. the technology priorities are: 1 100base-tx, half-duplex 2 10base-t half-duplex once auto-negotiation is complete, the status register reflects the actual speed that was chosen. p arallel d etection the transceiver also checks for 10base-t nlp or 100base-tx idle symbols. if either is detected, the device automatically configures to match the detected operating speed in half-duplex mode. this ability allows the device to communicate with legacy 10base-t and 100base-tx systems. c arrier s ense /rxdv for mii p ort o nly carrier sense is asserted asynchronously on the crs pins as soon as activity is detected on the receive data stream. rx_dv is asserted as soon as a valid ssd (start-of-stream delimiter) is detected. carrier sense and rx_dv are de- asserted synchronously upon detection of a valid end of stream delimiter or two consecutive idle code groups in the receive data stream. if carrier sense is asserted and a valid ssd is not detected immediately, rx_er is asserted instead of rx_dv. in 10base-t mode, carrier sense is asserted asynchronously on the crs pin when valid preamble activity is detected on the rxip/rxin pins. in half-duplex mode, the crs is activated during transmit and receive of data. c able l ength m onitor the ac208 can also detect the length of the cable and display the result in the interrupt control/status register (such as, 0000 stands for less than 10m cable used, 0001 stands for ~ 10m of cable, and 1111 stands for 150m cable).
ac208 preliminary data sheet 07/08/02 broadcom page 6 bridge function document ac208-ds04-405-r b ridge f unction m edia i ndependent i nterface the bridge supports mii for 10/100 mbps. port 0 of bridge can support either 10 or 100, while port 1 supports only at 100 mbps. refer to the mode pin table to configure port 0. f orwarding s cheme the bridge supports the store-and-forward scheme only. it does not support cut-through-mode. with store-and-forward, the incoming packet should be completely received to the buffer without error before it can be sent out. a ddress r ecognition the self-learning bridge function is based on source address field of packets. the bridge uses the xor hashing algorithm to address look-up table. programmable aging time and fast aging control is supported. r eset and r estart at power on, the bridge initially goes to the sram self-test mode. it generates eight patterns to evaluate sram status. m edia a ccess c ontrol the bridge media access control (mac) complies with certai n ieee 802.3 mac protocols such as frame formatting and collision handling, but does not generate crc codes. it generates a 56-bit preamble and start of frame delimiter while a packet is sending. in half-duplex mode, the device listens before transmitting, to prevent traffic jam. during collision, a pac ket is retransmitted at a random time.
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r initialization and setup page 7 i nitialization and s etup h ardware c onfiguration several different states of operation can be chosen through hardware configuration. external pins may be pulled high or low at reset time. the combination of high and low values determines the power on state of the device. many of these pins are multi-function pins which change their meaning when reset ends. s oftware c onfiguration several different states of transceiver operation may be chosen through the mdc/mdio interface. for details, see ?register descriptions? on page 18 . led s using an led display matrix with a refresh technique, onl y 16 pins are required to drive up to 48 leds with unique information. on, off, and flash states are used to indicate different information. with a reduced number of signals, the led display is easier to route on the board, and less costly. the active-low led data is driven out of led_d[0:7] pins for each port and the corresponding led functions are led_ln[5:0] pin. for details, see ?led display/configuration/prom interface? on page 16 and ?led display matrix? on page 38 . the ac208 supports two leds per port. the following table describes how each of the led is connected. signals led_d[0:7] are indicators of port 1 through 8. signals led_ln[0:5] are events driven of port 1 through 8.
ac208 preliminary data sheet 07/08/02 broadcom page 8 initialization and setup document ac208-ds04-405-r table 1: led connections signals events descriptions led_ln[0] link status/activity active low indicates 100m link is good. blinking indicates 100m activity. led_ln[1] speed/partition active low indicates 10m link is good. blinking indicates 10m activity. led_ln[2] display utilization on bridge segment a (100 mbps) led_ln[2] is active low, indicating 100m utilization. utilization indicator is not per port basis, but rather per segment basis. the led_d[0:7] indicates percentage of utilization. led_d[0:7]76543210 percent util. non non 85% 65% 45% 25% 12% 1% led_ln[3] display utilization on bridge segment b (10 mbps) led_ln[3] is active low, indicating 10m utilization. utilization indicator is not per port basis, but rather per segment basis. the led_d[0:7] indicates percentage of utilization. led_d[0:7]76543210 percent util. non non non 65% 45% 25% 12% 1% led_ln[4] display collision on bridge segment a (100 mbps) led_ln[4] is active low, indicating collision. collision indicator is not per port basis, but rather per segment basis. the led_d[1:7] indicates percentage of collision. however, led_d0 only indicates collision occurrence. led_d[0:7]76543210 percent col. 66% 32% 16% 8% 4% 2% 1% col. led_ln[5] display collision on bridge segment b (10 mbps) led_ln[5] is active low, indicating collision. collision indicator is not per port basis, but rather per segment basis. the led_d[1:7] indicates percentage of collision. however, led_d0 only indicates collision occurrence. led_d[0:7]76543210 percent col. 66% 32% 16% 8% 4% 2% 1% col.
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r addressing algorithm, routing, learning, and aging page 9 a ddressing a lgorithm , r outing , l earning , and a ging a ddress t able the address table can store up to 1k entries and each entry consists of 48-bit mac address, 8-bit port identifier, 1-bit indication flag and 6-bit aging timer. bit 30: entry valid/empty indication, 1 = valid entry, 0 = empty entry. bit 29-24: aging timer. bit 23-16: port number table 2: content of address lookup table 3130 0 v timer port# mac#1 mac#2 mac#3 mac#4 mac#5 mac#6
ac208 preliminary data sheet 07/08/02 broadcom page 10 addressing algorithm, routing, learning, and aging document ac208-ds04-405-r a ddress r ecognition the exclusive or addressing algorithm is used for address lookup table addressing (see the following figure). figure 2: exclusive or hashing algorithm the final address of address lookup table is the hashed address[9:0]. r outing d ecision if a record is empty, the packet is broadcast and treated as an unknown frame. otherwise, the record is read, and compared with the current da. if two addresses are the same, the port number is decided, and the packet is forwarded to the assigned port. if address collision occurred, different mac address, the incoming packet is considered an unknown packet. l earning p rocess the address learning process is composed of the sa packets and the addressing algorithm described above. the bridge checks each incoming packets integrity and buffers availability. if a packet is error-free and the buffer is available, the sa/ port number pair of the packet is written into the address lookup table. the following figure describes the general operations of address learning and recognition. figure 3: address learning and recognition a ging t ime the switch automatically examines the status of address lookup table. the round robin speed and checking timer are dependent on the aging time. the switch aging time is set at 300s. when the aging timer is started after power on, the switch guaranties that free spaces can be released from occupied address entries. mac#6 mac#4 mac#2 xor xor = hashed address[15:0] mac#5 mac#3 mac#1 xor xor = xor hashing function da or sa [9:0] address entry point aaa-1 aaa aaa+1 address lookup tbl
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r addressing algorithm, routing, learning, and aging page 11 f orwarding s cheme the store-and-forward algorithm is used. the incoming packet has to be completely stored in the buffer and verified error- free before forwarding operations take place. b ridge b uffer m anagement and q ueues the bridge buffering management continues to store received packets into memory. the buffer size for 100m port is 16k bytes, and 8k bytes for 10m port. figure 4: basic memory management concept the bridge uses the six pointers to control per port buffer status. start address point is the beginning of memory address for each port and the end address point is the last address of memory for each port. the read/write and shadow read/write pointers are dynamically changed depending on the current outgoing and incoming packets in the storage. if the write pointer reaches the read pointer and the size between write and read pointers is smaller than 2k bytes, buffer is full. on the other hand, when read/write pointers are equal, the buffer is empty. table 3: embedded memory structure 31 0 0x0000 2k x 32 for address lookup table 0x07ff 0x0800 4k x 32 for 100m bridge port 0x17ff 0x1800 2k x 32 for 10m bridge port 0x1fff write point end address start address read point free buffer per port buffer management
ac208 preliminary data sheet 07/08/02 broadcom page 12 pins document ac208-ds04-405-r section 2: pins p in d escriptions many of these device pins have multiple functions. the separate descriptions of each pin are listed in the proper sections. designers must assure that they have identified all modes of operation prior to final design. the media dependent interface (mdi) pin assignment shown below and in the pin description table is subject to change without notice. the user is advised to contact altima communications, inc. before implementing any design based on the information provided in this data sheet. signals types: i = input o = output z = high impedance u = pull up with 10 k ? d = pull down with 10 k ? s = schimitt trigger a = analog signal p = power g = ground * = active low signal table 4: media dependent interface pins (tx) pin name pin # type description rxip_7 rxip_6 rxip_5 rxip_4 rxip_3 rxip_2 rxip_1 rxip_0 107 96 95 84 83 72 71 60 ai ai ai ai ai ai ai ai receiver input positive for both 10base-t and 100base-tx. rxin_7 rxin_6 rxin_5 rxin_4 rxin_3 rxin_2 rxin_1 rxin_0 106 97 94 85 82 73 70 61 ai ai ai ai ai ai ai ai receiver input negative for both 10base-t and 100base-tx.
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r pin descriptions page 13 txop_7 txop_6 txop_5 txop_4 txop_3 txop_2 txop_1 txop_0 104 99 92 87 80 75 68 63 ao ao ao ao ao ao ao ao transmitter output positive for both 10base-t and 100base-tx. txon_7 txon_6 txon_5 txon_4 txon_3 txon_2 txon_1 txon_0 103 100 91 88 79 76 67 64 ao ao ao ao ao ao ao ao transmitter output negative for both 10base-t and 100base-tx. table 5: eeprom interface pin name pin # type description prom_cs 127 o prom chip select. connected to chip select pin of 93c46 serial eeprom prom_clk led_d[6] 124 o prom clock. connected to clk pin of 93c46 serial eeprom prom_out led_d[5] 123 o prom data out. connected to data_in pin of 93c46 serial eeprom prom_in led_d[7] 125 i,d prom data in. connected to data_out pin of 93c46 serial eeprom table 6: mdc/mdio interface pin name pin # type description mdc (prom_cs) 127 i,u clock signal between the external device and phy registers for communication synchronization mdio 128 i/o,d data input/output. it is a bi-directional data interface used by the external device to access only the internal phy registers within the ac208. this pin has internal pull-down register. table 4: media dependent interface pins (tx) (cont.) pin name pin # type description
ac208 preliminary data sheet 07/08/02 broadcom page 14 pin descriptions document ac208-ds04-405-r table 7: 100 mbps internal repeater pin name pin # type description m100col_local* 3 i/o, u 100m local collision. input when chipid = 00. active low to indicate collision on all other chipids. m100acto* 4 o, u output to chipid=00 for chipid 00 to signal local activity. this signal is pure combinational logic and is not in sync with any clock source. (refer to next 3 signals). m100acti_0* (m100acto*) 4 i,u input for chipid=00 from chipid 00 m100acto* pins to indicate activities. open on all other chipids. m100acti_1* 6 i,u connected from chipid=00 to chipid=10 m100acto* to sense activities. open on all other chipids. m100acti_2* 7 i,u connected from chipid=00 to chipid=11 m100acto* to sense activities. open on all other chipids. m100col_sys* 2 i/o,u chipid=00 drives this pin the same as 100colbp* to indicate local collision. m100crs_sys* 8 i/o,u chipid=00 drives this pin the same as 100crsbp* to indicate local activity. ms100d4 ms100d3 ms100d2 ms100d1 ms100d0 14 13 12 11 9 i/o,d i/o,d i/o,d i/o,d i/o,d multiple/stacked data group. transmit and receive data in de- scrambled 5b data groups for multiple devices. data is sampled at the rising edge of ms100d_clk and driven out on falling edge of ms100d_clk. ms100d_en* 1 i/o,u multiple/stacked data enable. active-low when data is valid. signal is driven out on the falling edge of ms100d_clk, and sampled at the rising edge of ms100d_clk. ms100d_clk 16 i/o, u, s multiple/stacked data clock. the bi-directional non-continuous 25 mhz recovered clock for synchronizing with ms100d[4:0], and ms100d_en*.
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r pin descriptions page 15 table 8: 10 mbps internal repeater bus pin name pin # type description m10col_local* 18 i/o, u 10m local collision. input when chipid = 00. active low to indicate collision on all other chipids. m10col_local# (local_collision). m10acto* 19 o, u output to chipid = 00 for chipid 00 to signal local activity. (refer to next 3 signals). m10acti_0* (m10acto*) 19 i,u connected from chipid = 00 from chipid = 01 m10acto* to sense activities. open on all other chipids. m10acti_1* 20 i,u connected from chipid 00 to chipid 10 m10acto* to sense activities. open on all other chipids. m10acti_2* 21 i,u connected from chipid 00 to chipid 11 m10acto* to sense activities. open on all other chipids. m10col_sys* 27 i/o,u chipid 00 drives this pin the same as 10colbp* to indicate system collision. m10crs_sys* 22 i/o,u chipid 00 drives this pin the same as 10crsbp* to indicate system activity. ms10d 25 i/o,d multiple/stacked data group. transmit and receive data in 10base-t for multiple devices. data is sampled at the rising edge of ms10d_clk and driven out on falling edge of ms10d_clk. ms10d_en* 26 i/o,u multiple/stacked data enable. active when data is valid. ms10d_clk 24 i/o, u, s multiple/stacked data clock. the bi-directional non-continuous 10 mhz recovered clock for synchronizing with ms10d and ms10d_en*.
ac208 preliminary data sheet 07/08/02 broadcom page 16 pin descriptions document ac208-ds04-405-r led d isplay /c onfiguration /prom i nterface the led pins are shared with reset-read configuration pins, test pins and eeprom interface. the value applied on the reset-read pins is only valid at the end of the reset cycle. the eeprom interface is active after the reset cycle. once the data in the eeprom is read, the same pins are used for led display. forty-eight led outputs are available through an 6x8 matrix. table 9: led pins pin name pin # type description led_ln[5] led_ln[4] led_ln[3] led_ln[2] led_ln[1] led_ln[0] 50 51 52 53 54 55 o 48 ma enable corresponding led display line in the display matrix, active low output. the detail of how to program and connect the leds is in the led setup section. led_ln*[5] = display 10base-t collision rate and segment collision status. led_ln*[4] = display 100 mbps collision rate and segment collision status led_ln*[3] = display 10m segment utilization rate led_ln*[2] = display 100m segment utilization rate led_ln*[1] = programmable led display. the default is to display 10m link/activity information of each port. led_ln*[0] = programmable led display. the default is to display 100m link/activity information of each port. led_d[7] led_d[6] led_d[5] led_d[4] led_d[3] led_d[2] led_d[1] led_d[0] 125 124 123 122 121 120 119 118 i/o, d output for led display information of each column in the display matrix. active high output.
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r pin descriptions page 17 table 10: configuration and setup pin name pin # type description mode[3] mode[2] (led_d[4]) mode[1] (led_d[1]) mode[0] (led_d[0]) 37 122 119 118 i,d mode[1:0] domain a domain b 00 100m rptr 10m rptr (master) 01 100m rptr 10m rptr (slave, bridge disable ) 10 100m port 7 11 100m rptr 10m rptr ( slave, bridge, enable and 10m disable) mode[3:2] mii reserved tp125 36 i 1:select 1:1.25 xformer chipid[0] (led_d[3]) chipid[1] (led_d[2]) 120 121 i,d to assign chip id for four devices in a single box. one device in the box must be assigned with chipid = 0. rbp 112 i reference bias resistor. connected to analog ground through a 10k (1%) resistor. table 11: clock reset pin name pin # type description 1 reset* 1 47 1 i,u 1 reset to initial and defaulted state. pulse must be greater than 10 ns. 1 clk 1 48 1 i 1 25-mhz system clock reference input. this pin shall be connected to an external 25-mhz clock source. multiple devices should be synchronous to the same external clock source. table 12: power and ground pin name pin # type description dvcc 115, 126, 10, 23, 39, 46 p 2.5v power for digital circuit, total of 9 pins. dgnd 114, 116, 117, 5, 15, 32, 45, 49 g ground for digital circuit, total 10 pins. avcc 108, 109, 110, 57, 58, 59 p 2.5v power for analog circuit, total 16 pins. agnd 105, 62, 65, 66, 69, 74, 77, 78, 81, 86, 89, 90, 93, 98, 101, 102 g ground for analog circuit, total 16 pins gavdd 113 p 2.5v power supply for common analog circuit gagnd 111, 56 g ground for common analog circuit table 13: no connects pin name pin # type description n/c 17, 28, 29, 30, 31, 33, 34, 35, 38, 40, 41, 42, 43, 44 n/c no connects
ac208 preliminary data sheet 07/08/02 broadcom page 18 register descriptions document ac208-ds04-405-r section 3: register descriptions the following standard registers are supported. (register numbers are in decimal format, the values are in hex format). r egister d escription the following table lists the ac208 register sets. each register contains 16-bit data. the addresses in the following table are hexadecimal. note when writing to registers, it is recommended that a read/modify/write operation be performed, as unintended bits may get set to unwanted states. this applies to all registers, including those with reserved bits. table 14: register set phy addr offset addr definition type default 8 0?4 phy port status registers 8 0 phy port link status ro 8 1 phy port polarity status ro 8 2 phy port partition status for 100 mb ro 8 3 phy port partition status for 10 mb ro 8 4 phy port speed status ro 8 5 phy port isolation status ro 8 6 initial device configuration register r/w 8 7 bridge configuration register r/w 8 8 device revision number ro 0 0?31 phy 1 registers 0 0 phy control register r/w 3000 0 1 phy status register ro 2849 0 2 phy identifier 1 register ro 0022 0 3 phy identifier 2 register ro 5541 0 4 auto-negotiation advertisement register ro 00a1 0 5 auto-negotiation link partner ability register ro 0001 0 6 auto-negotiation expansion register ro 0004 0 7 auto negotiation next page transmit register ro 2001 0 8?15 reserved 0000 0 16 phy 10base-t configuration register control register r/w 0 17 phy interrupt control/status register 0 18 diagnostic register
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r register description page 19 019reserved ro 0 20 cable length register ro 0 21 receive error count 0 22 power management register 0 23 transceiver mode register 0 24?31 reserved 1 0?31 phy 2 registers 2 0?31 phy 3 registers 3 0?31 phy 4 registers 4 0?31 phy 5 registers 5 0?31 phy 6 registers 6 0?31 phy 7 registers 7 0?31 phy 8 registers 8 0?31 led effect registers 816 reserved 8 17 reserved ro 0000 8 18 led effect with partition/isolation event r/w 8 19 led effect with link event r/w 8 20 led effect with activity (crs) event r/w 8 21 led effect with autoneg event r/w 8 22 led effect with speed100 event r/w 8 23 led register control mode r/w table 14: register set (cont.) phy addr offset addr definition type default
ac208 preliminary data sheet 07/08/02 broadcom page 20 register description document ac208-ds04-405-r phy p ort s tatus r egister table 15: phy port status register name type address description phy port link status r 00 1 = link good 0 = default phy port polarity status r 01 1 = the polarity has been crossed 0 = default phy port partition status for 100 mb r 02 1 = the port has been partitioned 0 = default phy port partition status for 10 mb r 03 1 = the port has been partitioned 0 = default phy port speed status r 04 1 = 100m 0 = 10m 0 = default phy port isolation status (fast ethernet only) r 05 1 = the port has been isolated 0 = default table 16: phy port status 15:9 8 7 6 5 4 3 2 1 0 rsv mii rsv port 5 port 4 port 3 port 2 port 1 rsv rsv
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r register description page 21 i nitial d evice c onfiguration r egister table 17: initial device configuration register name type address description mii configuration r/w 06 used to give the status of mii port. default is set by pin. bit name type description default 15:12 mode ro mode[3:2] must be 00. mode pins mode[1:0] 00 master mode, bridge enable. 01 slave mode, bridge disable. 10 slave mode, uplink. port 7 is connected to the bridge port in this mode. the other bridge port is connected to 100 segment. 11 slave mode, bridge enable (mulit- bridge mode). 11 reserved (write clear enable) ro 10 reserved (mib enable) ro reserved. 0 9 disable partition r/w 1:disable partition function of mii interface. 0 8 external transform selection r/w 1:external transform 1:1.25, 0:external transform 1:1. ext pin 7 miib speed select r/w 1:100m interface, 0:10m interface. ext pin 6:2 switch debug r/w selection control for debugging signals. 00000 1 100m repeater partition alternative r/w 0 = normal, un-partition a port only when data can be transmitted out from the port for 560 bit-time without a collision. 1 = alternate, un-partition a port when data can be either transmitted from the port or received from the port for 560 bit-time without a collision. 0 0 10m repeater partition alternative r/w 0 = normal, un-partition a port when data can be either transmitted from the port or received from the port for 560 bit-time without a collision. 1 = alternate, un-partition a port only when data can be received from the port for 560 bit-time without a collision 0
ac208 preliminary data sheet 07/08/02 broadcom page 22 register description document ac208-ds04-405-r b ridge c onfiguration r egister table 18: bridge configuration register name type address description bridge configuration register r/w 07 used to configure bridge. bit name type description default 15 watch dog reset r/w 1 = reset when wdog even occur 0 = does not reset when wdog even occur 1 14 loose length r/w 1 = receives frame with length from 1519 to 1548 0 = rejects frame with length over 1518 1 13 dribble error r/w 1 = enable, 0:disable receive dribble error packets 0 12 address table initialization disable r/w 1 = disable, 0:enable address table init. while this bit is 1, the address table only contains few entries for speed up function verification. 0 11 aging speed up r/w 1 = enable, 0:disable aging speed up 0 10 10m back pressure r/w 1 = enable, 0:disable 10m back pressure function 0 9 100m back pressure r/w 1 = enable, 0:dieable 100m back pressure function 0 8 collision test r/w 1 = enable, 0:disable collision test 0 7:0 reserved r 00
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r phy registers page 23 phy r egisters the following registers are defined for each phy port. the base addresses of phy 1 to phy 8 are 0, 1, 2, 3, 4, 5, 6, and 7, respectively. phy c onfiguration r egister table 19: phy configuration register 0 bit name definition mode default 0.15 reset 1 = phy reset this bit is self-clearing. rw/sc 0 0.14 loopback 1 = loopback mode. because it internally loops the transmit of ac208 to its receive, it ignores all the activity on the cable media. 0 = normal operation. rw 0 0.13 speed select 1 = 100 mbps 0 = 10 mbps. this bit is ignored if auto-negotiation is enabled. it no longer reflects auto-negotiation results. rw 1 0.12 auto-neg enable 1 = enable auto-negotiate process (overrides 0.13 and 0.8) 0 = disable auto-negotiate process. in force mode, speed is selected via bit 0.13. rw 1 0.11 power down 1 = power down mode, puts ac208 in low-power stand-by mode, only reacts to access transaction. 0 = normal operation. rw 0 0.10 isolate 1 = electrical isolation of phy from mii and cable media. 0 = normal operation. rw 0 0.9 restart auto- negotiation 1 = restart auto-negotiation process. 0 = normal operation. rw/ sc 0 0.8 duplex mode 1 = full-duplex. 0 = half-duplex. full-duplex is not supported on this chip. it no longer reflects auto-negotiation results. ro 0 0.7 collision test 1 = enable collision test, which issues the col signal in response to the assertion of tx_en signal. 0 = disable col test. rw 0 0.6:0 reserved ro 000000
ac208 preliminary data sheet 07/08/02 broadcom page 24 phy registers document ac208-ds04-405-r phy s tatus r egister table 20: phy status register 1 bit name definition mode default 1.15 100base-t4 tied to 0 indicates no 100base-t4 capability. ro 0 1.14 100base-tx full-duplex tied to 0 indicates no 100base-tx full-duplex support. ro 0 1.13 100base-tx half-duplex 1 = 100base-tx with half-duplex. 0 = no tx half-duplex ability. ro 1 1.12 10base-t full- duplex tied to 0 indicates no 10base-t full-duplex support. ro 0 1.11 10base-t half- duplex 1 = 10base-t with half-duplex. 0 = no 10base-t half-duplex ability. ro 1 1.10:6 reserved ro 00001 1.5 auto-negotiate complete 1 = auto-negotiate process completed, indicates reg. 4, 5, 6 are valid. 0 = auto-negotiate process not completed. ro n/a 1.4 remote fault 1 = remote fault condition detected. 0 = no remote fault. after this bit is set, it remains set until it is cleared by reading register 1 via the mdc/mdio interface. sc/lh n/a 1.3 auto-negotiate ability 1 = able to perform auto-negotiation function, its value is determined by anega pin. 0 = unable to perform auto-negotiation function. ro 1 1.2 link status 1 = link is established. if ac208 link fails, this bit becomes cleared and remains cleared until register is read via the mdc/ mdio interface. 0 = link is down, or has been dropped. sc/ll 0 1.1 jabber detect 1 = jabber condition detect. 0 = no jabber condition detected. sc/lh 0 1.0 extended capability 1 = extended register capable. this bit is tied permanently to one. ro 1 1.15 100base-t4 tied to 0 indicates no 100base-t4 capability. ro 0
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r phy registers page 25 phy i dentifier 1 r egister phy i dentifier 2 r egister a uto -n egotiation a dvertisement r egister table 21: phy identifier 1 register register bit name description mode default 2.15:0 oui* assigned to the third through eighteenth bits of the organizationally unique identifier (oui). ro 0022 (hex) table 22: phy identifier 2 register register bit name description mode default 3.15:10 oui assigned to the nineteenth through twenty-fourth bits of the oui. ro 010101 3.9:4 model number six bit manufacturer?s model number; 101 is encoded as 010001. ro 010100 3.3:0 revision number four bits manufacturer?s revision number. 0001 stands for rev. a, and so on. ro 0001 table 23: auto-negotiation advertisement register bit name definition mode default 4.15 next page 1 = desire next page. 0 = next page is not desired. rw 0 4.14 acknowledge this bit is set internally after receiving three consecutive and consistent flp bursts. ro 0 4.13 remote fault 1 = remote fault detected. 0 = no remote fault. rw 0 4.12:10 reserved for future technology. rw 000 4.9 100base-t4 tied to 0 indicates no 100base-t4 support. ro 0 4.8 100base-tx full-duplex 1 = 100base-tx with full-duplex. 0 = no 100base-tx full-duplex ability. ro 0 4.7 100base-tx 1 = 100base-tx capable. 0 = no 100base-tx capability. rw 1 4.6 10base-t full- duplex 1 = 10 mbps with full-duplex. 0 = no 10 mbps with full-duplex capability. ro 0 4.5 10base-t 1 = 10 mbps capable. 0 = no 10 mbps capability. rw 1 4.4:0 selector field [00001] = ieee 802.3. ro 00001
ac208 preliminary data sheet 07/08/02 broadcom page 26 phy registers document ac208-ds04-405-r a uto -n egotiation l ink p artner a bility r egister a uto -n egotiation e xpansion r egister table 24: auto-negotiation link partner ability register register bit name description mode default 5.15:0 technology technology capability field, which indicates the technology capability of link partner. the bit definition is the same as reg. 4.15:0. ro 0001(h) table 25: register 6: auto-negotiation expansion register register bit name description mode default 6.15:5 reserved ro 0000 0000 000 6.4 parallel detection fault 1 = fault detected by parallel detection logic. this is caused by unstable link, or concurrent link up condition. 0 = no fault detected by parallel detection logic. sc/lh 0 6.3 link partner next page able 1 = link partner supports next page function. 0 = link partner does not support next page function. ro 0 6.2 next page able ro 1 6.1 page received 1 = a new link code word has been received. the contains of the received link code word is located in register 5. sc/lh 0 6.0 link partner auto-negotiation able 1 = link partner is auto-negotiation able. 1 = link partner is not auto-negotiation able. ro 0
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r phy registers page 27 a uto -n egotiation n ext p age t ransmit r egister table 26: auto-negotiation next page transmit register register bit name description mode default 7.15 np 1 = another next page is desired. rw 0 7.14 reserved ro 0 7.13 message page 1 = message page. 0 = un-formatted page. rw 1 7.12 ack2 acknowledge2. 1 = complies with message. 0 = can not comply with message. rw 0 7.11 toggle 1 = previous value of transmitted link code word equal to 0. 0 = previous value of transmitted link code word equal to 1. ro n/a 7:10:0 code message/un-formatted code field. rw 0001
ac208 preliminary data sheet 07/08/02 broadcom page 28 phy registers document ac208-ds04-405-r phy 10base-t c onfiguration r egister table 27: phy 10base-t configuration register register bit name description mode default 16.15 repeater 1 = repeater mode. full-duplex is inactive, and ces only responses to receive activity. seq test function is also disabled. 0 = dte mode. rw 1 16.14 reserved ro 0 16.13 txjam 1=force cim to send jam pattern. 0=normal operation mode ro 0 16.12 cim disable 1 = disable carrier integrity monitor function. 0 = enable carrier integrity monitor function. default is ?0?. rw 1 16.11 seq test inhibit 1 = disable 10base-t seq testing. 0 = enable 10base-t seq testing. generates a col pulse following the completion of a packet transmission. rw 0 16.10 base-t normal loop back 1 = enable 10base-t normal loop back. 0 = disable 10base-t normal loop back. rw 0 16.[9:6] reserved ro 0 16:5 auto polarity disable 1 = disable auto polarity detection/correction. 0 = enable auto polarity detection/correction. rw 0 16.4 reverse polarity when reg16.5 is set to 0, this bit sets to 1. if reverse polarity is detected on the media, it is set to 0. when reg16.5 is set to 1, writing a one to the bit reverses the polarity of the transmitter. note: the reverse polarity is detected either through 8 inverted nlp or through a burst of inverted flp. rw 0 16:[3:0] reserved ro 0
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r phy registers page 29 phy i nterrupt c ontrol /s tatus r egister table 28: phy interrupt control/status register register bit name description mode default 17.15 jabber_ie jabber interrupt enable. rw 0 17.14 rx_er_ie receive error interrupt enable. rw 0 17.13 page_rx_ie page received interrupt enable. rw 0 17.12 pd_fault_ie parallel detection fault interrupt enable. rw 0 17.11 lp_ack_ie link partner acknowledge interrupt enable. rw 0 17.10 link_schange_ ie link status changed interrupt enable. rw 0 17.9 r_fault_ie remote fault interrupt enable. rw 0 17.8 aneg_comp_ie auto-neg complete interrupt enable. rw 0 17.7 jabber_int this bit is set when a jabber event is detected. rc 0 17.6 rx_er_int this bit is set when rx_er transitions high. rc 0 17.5 page_rx_int this bit is set when a new page is received from link partner during auto-negotiation. rc 0 17.4 pd_fault_int this bit is set when parallel detect fault is detected. rc 0 17.3 lp_ack_int this bit is set when the flp with acknowledge bit set is received. rc 0 17.2 link_schanged int this bit is set when link status is changed. rc 0 17.1 r_fault_int this bit is set when remote fault is detected. rc 0 17.0 a_neg_comp int this bit is set when auto-neg is completed. rc 0
ac208 preliminary data sheet 07/08/02 broadcom page 30 phy registers document ac208-ds04-405-r d iagnostic r egister c able l ength r egister table 29: diagnostic register register bit name description mode default 18.15 lp_lpbk link pulse loopback. 1 = loopback the link pulse for auto-negotiation testing rw 0 18.14 send_nlp 1 = force link pulse generator to send nlp event in auto-negotiation mode. rw 0 18.13 force link pass bt 1 = force 10base-t link pass rw 0 18.12 force link pass tx 1 = force 100 tx link pass rw 0 18.11 dplx this bit indicates the result of the auto-neg for duplex arbitration. ro 0 18.10 speed this bit indicates the result of the auto-neg for data speed arbitration. ro x 18.9 rx_pass in 10base-t mode, this bit indicates that manchester data has been detected. in 100base-t mode, it indicates valid signal has been received but not necessarily locked on to. rc x 18.8 rx_lock indicates the receive pll has locked onto the received signal for the selected speed of operation (10base-t or 100base-tx). this bit is set whenever a cycle-slip occurs, and will remain set until it is read. rc x 18.[7:4] arb_state highest highest state of auto-negotiation state machine since reset on last read operation. rc tbd 18.[3:0] arb_state lowest lowest state of auto-negotiation state machine since reset on last read operation. rc tbd table 30: cable length register register bit name description mode default 20.[15:9] reserved ro 0000000 20.8 adaptation disable 1 = disable adaptation rw 0 20.[7:4] cable length indication these bits indicate cable length from 0 to 150m. each bit represents 10m. for example, if the cable length is 100m then bits [7:4] = 1010. these bits are only applicable to 100tx mode. rw xxxx 20.[3:0] adaptation low limit adaptation setting, when sd signal is first detected. ro xxxx
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r phy registers page 31 r eceive e rror c ount p ower m anagement r egister table 31: receive error count register bit name description mode default 21.[15:0 ] receive error count count number of receiving packets with error. this register can only be cleared by reset (software or hardware). ro 0000 table 32: power management register register bit name description mode default 22.[15:14] reserved ro 00 22.13 pd_pll 1=power down pll circuit ro x 22.12 pd_equal 1=power down equalizer circuit ro x 22.11 pd_bt_rcvr 1=power down 10base-t receiver ro x 22.10 pd_lp 1=power down link pulse receiver ro x 22.9 pd_en_det 1=power down energy detect circuit ro x 22.8 pd_fx 1=power down fx circuit ro x 22.[7:6] reserved rw 00 22.5 msk_pll 0=force power up pll circuit rw x 22.4 msk_equal 0=force power up equalizer circuit rw x 22.3 msk_bt_rcvr 0=force power up 10base-t receiver rw x 22.2 msk_lp 0=force power up link pulse receiver rw x 22.1 msk_en_det 0=force power up energy detect circuit rw x 22.0 msk_fx 0=force power up fx circuit rw x
ac208 preliminary data sheet 07/08/02 broadcom page 32 phy registers document ac208-ds04-405-r t ransceiver m ode r egister table 33: transceiver mode register register bit name description mode default 23.15 reserved ro 0 23.14 reserved ro 0 23.13 clk_rclk_save 1 = set rclk save mode. rclk is hut off after 64 cycles of each packet rw 0 23.12 reserved ro 0 23.11 scramble disable 1 = disable scrambler rw 0 23.10 serial bt enable 1 = enable serial bt mode rw 0 23.9 pcsbp 1 = enable pcs bypass mode rw 0 23:8 age timer en 1 = enable age timer in adaptation 0 = disable age timer in adaptation. rw 0 23.7 reserved ro 0 23:6 reserved ro 0 23.5 force re-adapt 1 = force adaptation to re-adapt writing a 1 to this bit forces adaptation to re-adapt. this bit is always read as 0. ro 0 23.[4:0] dlock drop counter d lock drop counter ro xxxxx
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r test and led effect register page 33 t est and led e ffect r egister this set of the registers is defined for the whole chip. the base address is hex 08. led e ffect with p artition /i solation e vent led e ffect with l ink e vent table 34: led effect with partition/isolation event register bit name description mode default 15:12 blink rate [7:4] set the blink rate bits [7:0] with led effect with partition/isolation event register (phy addr = 8; reg addr = 18), abbreviated as reg_led_effect in the following equation. blink rate = 1 / (16 ms x {reg_led_effect[15:12], 4?b0000} x 2) rw 0001 11:10 reserved ro 00 9:8 led on with part/iso event when partition/isolation, turn on corresponding led 1:0. rw 00 7:6 reserved ro 00 5:4 led blink with part/iso event when partition/isolation, blink corresponding led 1:0. rw 00 3:2 reserved ro 00 1:0 led off with part/iso event when partition/isolation, turn off corresponding led 1:0. rw 00 table 35: led effect with link event register bit name description mode default 15:10 reserved ro 00000 9:8 led on with link event when link up, turn on corresponding led 1:0. rw 11 7:6 reserved ro 00 5:4 led blink with link event when link up, blink corresponding led 1:0. rw 11 3:2 reserved ro 00 1:0 led off with link event when link up, turn off corresponding led 1:0. rw 00
ac208 preliminary data sheet 07/08/02 broadcom page 34 test and led effect register document ac208-ds04-405-r led e ffect with a ctivity (crs) e vent led e ffect with a uto -n egotiating e vent table 36: led effect with activity (crs) event register bit name description mode default 15:10 reserved ro 00000 9:8 led on with activity event when activity, turn on corresponding led 1:0. rw 00 7:6 reserved ro 00 5:4 led blink with activity event when activity, blink corresponding led 1:0. rw 11 3:2 reserved ro 00 1:0 led off with activity event when activity, turn off corresponding led 1:0. rw 00 table 37: led effect with auto-negotiating event register bit name description mode default 15:10 reserved ro 00000 9:8 led on with auto- negotiating event when auto-negotiating, turn on corresponding led 1:0. rw 00 7:6 reserved ro 00 5:4 led blink with auto-negotiating event when auto-negotiating, blink corresponding led 1:0. rw 00 3:2 reserved ro 00 1:0 led off with auto- negotiating event when auto-negotiating, turn off corresponding led 1:0. rw 00
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r test and led effect register page 35 led e ffect with s peed 100 e vent led r egister c ontrol m ode table 38: led effect with speed100 event register bit name description mode default 15:10 reserved ro 00000 9:8 led on with speed100 event when speed100, turn on corresponding led 1:0. rw 01 7:6 reserved ro 00 5:4 led blink with speed100 event when speed100, blink corresponding led 1:0. rw 01 3:2 reserved ro 00 1:0 led off with speed100 event when speed100, turn off corresponding led 1:0. rw 10 table 39: led register control mode register bit name description mode default 15:8 led data set value shown on the led_d[7:0]. rw 000000 7:6 reserved ro 00 5:0 led column control which lane of the led_d should be turned on. rw 000000
ac208 preliminary data sheet 07/08/02 broadcom page 36 eeprom table document ac208-ds04-405-r eeprom t able eeprom is used to configure the initial setting of bridge, repeater, and transceiver. table 40: eeprom address description default assign to 0first word 5a3c 1 test configuration register0 0080 phy=8, reg=28 2 initial repeater configuration register 0180 phy=8, reg=6 3 bridge configuration register d000 phy=8, reg=7 4 initialize port 0 configuration register 3000 phy=0, reg=0 5 initialize port 1 configuration register 3000 phy=1, reg=0 6 initialize port 2 configuration register 3000 phy=2, reg=0 7 initialize port 3 configuration register 3000 phy=3, reg=0 8 initialize port 4 configuration register 3000 phy=4, reg=0 9 initialize port 5 configuration register 3000 phy=5, reg=0 10 initialize port 6 configuration register 3000 phy=6, reg=0 11 initialize port 7 configuration register 3000 phy=7, reg=0 12 led effect with partition/isolation event 1000 phy=8, reg=18 13 led effect with link event 0330 phy=8, reg=19 14 led effect with activity (crs) event 0030 phy=8, reg=20 15 led effect with autoneg event 0000 phy=8, reg=21 16 led effect with speed100 event 0200 phy=8, reg=22
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r eeprom table page 37 4b/5b c ode -g roup t able table 41: 4b/5b code-group table pcs code group[4:0] symbol name mii (txd/rxd [3:0]) description 11110 0 0000 data 0 01001 1 0001 data 1 10100 2 0010 data 2 10101 3 0011 data 3 01010 4 0100 data 4 01011 5 0101 data 5 01110 6 0110 data 6 01111 7 0111 data 7 10010 8 1000 data 8 10011 9 1001 data 9 10110 a 1010 data a 10111 b 1011 data b 11010 c 1100 data c 11011 d 1101 data d 11100 e 1110 data e 11101 f 1111 data f idle and control code 11111 i 0000 inter-packet idle; used as inter-stream fill code. 11000 j 0101 start of stream delimiter, part 1 of 2; always use in pair with k symbol. 10001 k 0101 start of stream delimiter, part 2 of 2; always use in pair with j symbol. 01101 t undefined end of stream delimiter, part 1 of 2; always use in pair with r symbol. 00111 r undefined end of stream delimiter, part 2 of 2; always use in pair with t symbol. invalid code 00100 h undefined transmit error; used to send halt code-group 00000 v undefined invalid code 00001 v undefined invalid code 00010 v undefined invalid code 00011 v undefined invalid code 00101 v undefined invalid code 00110 v undefined invalid code 01000 v undefined invalid code 01100 v undefined invalid code 10000 v undefined invalid code 11001 v undefined invalid code
ac208 preliminary data sheet 07/08/02 broadcom page 38 led display matrix document ac208-ds04-405-r led d isplay m atrix the led display uses refresh technique. by using the led di splay matrix, the number of ports to drive the led can be significantly reduced. two leds are assigned for each port. on , off, and flash states are used to indicate different information. with reduced led counts, and reduced number of signals, the led display will be easier to route on the board, and less costly. figure 5: led display matrix s ystem c onsiderations the design of the chip is optimized for low cost 10/100 mb unmanaged repeater applications. it also provides flexibility for systems that require multiple lan ports within the same unmanaged repeater domain. led_ln[5] led_d[0] led_ln[4] led_ln[3] led_ln[2] led_ln[1] led_ln[0] led_d[1] led_d[2] led_d[3] led_d[4] led_d[5] led_d[6] led_d[7] d? le d? le d? le d? le d? le d? le d le d le d le d le d le d le d le d le d le d le d le d le d? le d? le d? le d? le d? le d? le d le d le d le d le d le d le d le d le d le d le d le d le d? le d? le d le d le d? le d le d? le d? le d? le d le d le d le 330 ohm 330 ohm 330 ohm 330 ohm 330 ohm 330 ohm 330 ohm 330 ohm
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r electrical characteristics page 39 section 4: electrical characteristics the following electrical characteristics are design goals rather than characterized numbers. a bsolute m aximum r atings storage temperature............................... ?55 o c to +150 o c vcc supply referenced to gnd............. ?0.5v to 2.5v digital input voltage............................... ?0.5v to 3.3v dc output voltage.................................. ?0.5v to vcc o perating r ange operating temperature (ta)........................... 0 o c to 70 o c vcc supply voltage range (vcc).................. 2.375v to 2.625v table 42: total power consumption parameter symbol conditions minimum typical maximum units supply current (per port) icc 10base-t, idle 10base-t, normal activity 100base-tx 10/100base-tx, low power without cable power down 53 53 153 103 44 44 ma ma ma ma ma supply current (dual speed hub) icc mode 00 master mode 01 slave, bridge disabled mode 10 slave, uplink mode 11 slave, bridge enabled 680 620 680 680 ma ma ma
ac208 preliminary data sheet 07/08/02 broadcom page 40 operating range document ac208-ds04-405-r refclk p ins i/o c haracteristics ?led p ins table 43: ttl i/o characteristics parameter symbol conditions minimum typical maximum units input voltage high vih 2.0 v input voltage low vil 0.8 v input current ii ?10 10 ma output voltage high voh 2.0 v output voltage low vol 0.4 v output current high ioh 8 ma output current low iol -8 ma input capacitance ci 10 pf output transition time 3.15v < vcc < 3.45v 5 ns tristate leakage current |ioz| 10 ua table 44: refclk pins parameter symbol conditions minimum typical maximum units input voltage low vil 0.8 v input voltage high vih 2.0 v input clock frequency tolerance f 100 ppm input clock duty cycle tdc 40 60 % input capacitance cin 3.0 pf table 45: i/o characteristics?led pins parameter symbol conditions minimum typical maximum units output low voltage vol 0.4 v output high voltage voh v input current ii 27 ma output current io ma
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r operating range page 41 100base-tx t ransceiver c haracteristics 10base-t t ransceiver c haracteristics table 46: 100base-tx transceiver characteristics parameter symbol conditions minimum typical maximum units peak to peak differential output voltage vp note 1 1.9 2.0 2.1 v output voltage symmetry vss note 1 0.98 1.02 mv signal rise/fall time trf note 1 3.0 5.0 ns rise/fall time symmetry trfs note 1 0 0.5 ns duty cycle distortion dcd 0 0.5 ps overshoot/undershoot vos 5 % output jitter scrambled idle 1.4 ns receive jitter tolerance 4 ns output current high ioh 1:1 transformer 40 ma output current high ioh 1.25:1 transformer 32 ma common mode input voltage 1.25 v differential input resistance 4 k ? note 1: 50 ? ( 1%) resistor to vcc on each output table 47: 10base-t transceiver characteristics parameter symbol conditions minimum typical maximum units peak to peak differential output voltage vop note 1 4.4 5 5.6 v start of idle pulse width 300 350 ns output jitter 1.4 ns receive jitter tolerance 32 ns differential squelch threshold vds 300 400 500 mv common mode rejection 25 v note 1: 50 ? ( 1%) resistor to vcc on each output
ac208 preliminary data sheet 07/08/02 broadcom page 42 digital timing characteristics document ac208-ds04-405-r section 5: digital timing characteristics p ower on r eset figure 6: power on reset table 48: power on reset parameter symbol conditions minimu m typical maximu m units rst* low period trst 150 - - s configuration tconf 100 - - ns trst rst* tconf all configuration pins
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r phy mdc/mdio interface page 43 phy mdc/mdio i nterface figure 7: phy mdc/mdio interface table 49: phy mdc/mdio interface parameter symbol conditions minimum typical maximum units mdc clock tmdcl - 300 - ns mdc clock tmdch - 300 - ns receive data setup time trds setup on read cycle 10 - - ns receive data hold time trdh hold on read cycle 10 - - ns transmit data delay time ttdd delay on write cycle 3 - 18 ns mdc mdio ( in ) mdio (o ) tm d c l tm d c h tr d s tr d h tt d d
ac208 preliminary data sheet 07/08/02 broadcom page 44 100 mbps repeater backplane receive/transmit timing document ac208-ds04-405-r 100 mbps r epeater b ack p lane r eceive /t ransmit t iming figure 8: 100 mbps rbp receive/transmit timing table 50: 100 mbps repeater backplane receive/transmit timing parameter symbol minimum typical maximum units ms100d_clk period tck 40 ns ms100d_clk high period tckh 18 22 ns ms100d_clk low period tckl 18 22 ns rxip/n to control assert tjc 180 ns rxip/n to control de-assert ttc 180 ns rxip/n to m100col_sys* assert tccs 200 ns control falling to ms100crs_sys*/ ms100d_en falling delay time tcsc 30 ns ms100d to ms100d_clk rising setup time tds 12 ns ms100d to ms100d_clk rising hold time tdh 5 ns control assert to txop/n valid tclt 300 ns control de-assert to txop/n invalid tcht 200 control is the combination of the following signals: m100act0*, m100act1_0*, m100act1_1*, m100act1_2* tjc ttc tds tdh tclt tcht tccs tcsc rxip/n txop/n start of packet tck tckh tckl ms100d_clk control* end of packet ms100d m100col_sys* ms100crs_sys*/ ms100d_en*
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r 10 mbps repeater backplane receive/transmit timing page 45 10 mbps r epeater b ack p lane r eceive /t ransmit t iming figure 9: 10 mbps rbp receive/transmit timing table 51: 10 mbps repeater backplane receive/transmit timing parameter symbol minimum typical maximum units ms10d_clk period tck 100 ns ms10d_clk high period tckh 40 60 ns ms10d_clk low period tckl 40 60 ns rxip/n to control assert tjc 280 ns rxip/n to control de-assert ttc 280 ns rxip/n to c10col_sys* assert tccs 300 ns control falling to ms10crs_sys*/ms10d_en* falling delay time tcd 30 ns ms10d to m10d_clk rising setup time tds 20 ns ms10d to ms10d_clk rising hold time tdh 5 ns control assert to txop/n valid tclt 720 ns control de-assert to txop/n invalid tcht 4000 ns control is the combination of the following signals: m10act0*, m10act1_0*, m10act1_1*, m10act1_2* tjc ttc tds tdh tclt tcht tccs tcsc rxip/n txop/n tck tckh tckl ms10d_clk control* ms10d m10col_sys* ms10crs_sys*/ ms10d_en* sop eop
ac208 preliminary data sheet 07/08/02 broadcom page 46 eeprom interface timing document ac208-ds04-405-r eeprom i nterface t iming figure 10: eeprom interface timing table 52: eeprom interface timing parameter symbol conditions minimum typical maximum prom_clk period teck - 5120 - ns prom_clk low period teckl 2550 - 2570 ns prom_clk high period teckh 2550 - 2570 ns prom_in to prom_clk rising hold time terds 10 - - ns prom_in to prom_clk rising hold time terdh 10 - - ns prom_clk falling to prom_out output delay time tewdd - - 20 tewdd teck teckh teckl terds terdh prom_out prom_clk prom_cs prom_in
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r led timing page 47 led t iming figure 11: led timing table 53: led timing parameter symbol conditions minimum typical maximum units pulse width tpw 2 ms led_d[n] falling to led_d[n+1] falling tpp 2 ms led_d[n] falling to led_d[n] falling tpd 16 ms led_ln[5:0] led_d[7] led_d[6] led_d[5] led_d[4] led_d[3] led_d[2] led_d[1] led_d[0] tpw tpp tpd
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r tx application termination page 48 tx a pplication t ermination figure 12: application termination ac208 txon txop ibref rxip rxin 1 tx+ 2 tx- 3 rx+ 4 unused 5 unused 6 rx- 7 unused 8 unused rj45 txc_p tx+_p tx-_p rx+_p rx-_p rxc_p txc_s tx+_s tx-_s rx+_s rx-_s rxc_s transformer 2.5v chassis gnd 75 ? x 4 110 ? 1% 49.9 ? 1% 49.9 ? 1% 0.1 f 0.1 f 10 k ? 1% 1000 pf 3 kv
preliminary data sheet ac208 07/08/02 broadcom document ac208-ds04-405-r mechanical information page 49 section 6: mechanical information figure 13: 128-pin pqfp table 54: package dimensions for the ac208 n a a1 a2 b d d1 d2 e e1 e2 e l l1 128 3.40 max 0.25 min 2.70 0.2 0.200 0.1 23.20 0.25 20.00 0.10 18.5 0.10 17.20 0.25 14.00 0.10 12.50 0.10 0.50 0.88 0.2 1.60 0.12 d 1 d e 1 e e b l1 l a a2 a1 1 65 103 39 e 2 d 2
document ac208-ds04-405-r broadcom altima communications, inc. a wholly owned subsidiary of broadcom corporation p.o. box 57013 16215 alton parkway irvine, ca 92619-7013 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, f unction, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. ac208 preliminary data sheet 07/08/02 section 7: ordering information table 55: ordering information part number package ambient temperature ac208kqm 128-pin pqfp 0 to 70 c

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